Phys. Rev. Applied paper on combining Invertible Logic with Parallel Tempering for Maximum Satisfiability
Andrea and Navid's paper shows how invertible logic with p-bits can be useful to solve maximum satisfiability problems using sophisticated optimization algorithms such as parallel tempering.
The search for hardware-compatible strategies for solving nondeterministic polynomial time (NP)-hard combinatorial optimization problems (COPs) is an important challenge of today’s computing research because of their wide range of applications in real-world optimization problems. Here, we introduce an unconventional scalable approach to face maximum-satisfiability (MAX-SAT) problems that combines probabilistic computing with p-bits, parallel tempering, and the concept of invertible logic gates. We theoretically show the spintronic implementation of this approach based on a coupled set of Landau-Lifshitz-Gilbert equations, showing a potential path for energy efficient and very fast (p-bits exhibiting nanosecond timescale switching) architecture for the solution of COPs. The algorithm is benchmarked with hard MAX-SAT instances from the 2016 MAX-SAT competition (e.g., “HG-4SAT-V150-C1350-1.cnf,” which can be described with 2851 p-bits), including weighted MAX-SAT and maximum-cut problems.