Sparse Ising Machines with p-bits are out in Nature Electronics. Congratulations Navid and Andrea!
We are excited to share Sparse Ising Machines with p-bits are now out in Nature Electronics. Also check out the coverage by the College of Engineering.
Three take-aways from this paper:
(a) p-bits are abstractions and they have many different implementations. Even present-day CMOS technology in FPGAs can convincingly outperform optimized TPUs and GPUs in probabilistic sampling.
(b) Parallelizing combinatorial optimization problems (or MCMC) is not easy but it is possible through intelligent sparsification in hardware-aware architectures. No scaled hardware (take the human brain or the Intel i9) is all-to-all connected. These results show the tremendous potential of sparse, parallel and effectively asynchronous operation.
(c) Solving practical optimization problems such as Boolean Satisfiability efficiently is hard, SAT solvers have been optimized after decades of fine-tuning and development. This paper shows that even existing FPGA-based p-computers can come close (and sometimes beat) SAT solvers without any fine-tuning. In addition, as a model hard problem, we show that we can reliably factor integers up to 32-bits, far larger than similar attempts. Physical realizations of p-bits with, for example, magnetic technology hold even greater potential and may lead to success stories in domain-specific computing.
It is a pleasure to acknowledge co-authors, National Science Foundation, Xilinx and UCSB Institute of Energy Efficiency (IEE) that made this work possible.
